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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-13 04:12:12 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-13 04:12:12 +0000 |
| commit | 3b7ffc6ae75a98827880c85c5f78099a044c8e09 (patch) | |
| tree | 63a8e07a41c84237aa44a0db94b9a1491ad65008 /llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | |
| parent | a4be3eff5c957fb280dbcc693c5cd966e9e3c158 (diff) | |
| download | bcm5719-llvm-3b7ffc6ae75a98827880c85c5f78099a044c8e09.tar.gz bcm5719-llvm-3b7ffc6ae75a98827880c85c5f78099a044c8e09.zip | |
AMDGPU/GlobalISel: Fix assert on multi-return side effect intrinsics
llvm.amdgcn.else hits this.
llvm-svn: 371812
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index c1c515ab4af..23ca49b8a84 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -731,7 +731,7 @@ bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS( MachineFunction *MF = BB->getParent(); MachineRegisterInfo &MRI = MF->getRegInfo(); - unsigned IntrinsicID = I.getOperand(0).getIntrinsicID(); + unsigned IntrinsicID = I.getIntrinsicID(); switch (IntrinsicID) { case Intrinsic::amdgcn_exp: { int64_t Tgt = getConstant(MRI.getVRegDef(I.getOperand(1).getReg())); |
