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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-01-07 11:29:05 -0500 |
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committer | Matt Arsenault <arsenm2@gmail.com> | 2020-01-09 10:29:31 -0500 |
commit | 3952748ffdf017f83faddcb1240cb36cb4bb9c5b (patch) | |
tree | 020bf845b71ad0406ee1f6dad36f0d47e438fef1 /llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | |
parent | 0274ed9dc75a0efb2b6130122226ee45f7e57dde (diff) | |
download | bcm5719-llvm-3952748ffdf017f83faddcb1240cb36cb4bb9c5b.tar.gz bcm5719-llvm-3952748ffdf017f83faddcb1240cb36cb4bb9c5b.zip |
AMDGPU/GlobalISel: Fix add of neg inline constant pattern
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index a41c8f1a6a3..a632e7aece1 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -2097,6 +2097,12 @@ void AMDGPUInstructionSelector::renderTruncImm32(MachineInstrBuilder &MIB, MIB.addImm(CstVal.getValue()); } +void AMDGPUInstructionSelector::renderNegateImm(MachineInstrBuilder &MIB, + const MachineInstr &MI) const { + assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && "Expected G_CONSTANT"); + MIB.addImm(-MI.getOperand(1).getCImm()->getSExtValue()); +} + bool AMDGPUInstructionSelector::isInlineImmediate16(int64_t Imm) const { return AMDGPU::isInlinableLiteral16(Imm, STI.hasInv2PiInlineImm()); } |