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| author | Tom Stellard <thomas.stellard@amd.com> | 2017-01-31 15:24:11 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2017-01-31 15:24:11 +0000 |
| commit | 124f5cc8c2552fcf776b1c35d7a8497eb920f6ba (patch) | |
| tree | 8499a6a61d5d9434afb91921738ec4b555563f49 /llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | |
| parent | ec78fd11ca6acc2387854ec8dd3385c6bbbb2342 (diff) | |
| download | bcm5719-llvm-124f5cc8c2552fcf776b1c35d7a8497eb920f6ba.tar.gz bcm5719-llvm-124f5cc8c2552fcf776b1c35d7a8497eb920f6ba.zip | |
AMDGPU/SI: Fix inst-select-load-smrd.mir on some builds
Summary:
For some reason instructions are being inserted in the wrong order with some
builds. I'm not sure why this is happening.
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, tpr, llvm-commits
Differential Revision: https://reviews.llvm.org/D29325
llvm-svn: 293639
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 6e5e9825eb8..d133851c852 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -84,13 +84,19 @@ bool AMDGPUInstructionSelector::selectG_ADD(MachineInstr &I) const { DebugLoc DL = I.getDebugLoc(); + MachineOperand Lo1(getSubOperand64(I.getOperand(1), AMDGPU::sub0)); + MachineOperand Lo2(getSubOperand64(I.getOperand(2), AMDGPU::sub0)); + BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo) - .add(getSubOperand64(I.getOperand(1), AMDGPU::sub0)) - .add(getSubOperand64(I.getOperand(2), AMDGPU::sub0)); + .add(Lo1) + .add(Lo2); + + MachineOperand Hi1(getSubOperand64(I.getOperand(1), AMDGPU::sub1)); + MachineOperand Hi2(getSubOperand64(I.getOperand(2), AMDGPU::sub1)); BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi) - .add(getSubOperand64(I.getOperand(1), AMDGPU::sub1)) - .add(getSubOperand64(I.getOperand(2), AMDGPU::sub1)); + .add(Hi1) + .add(Hi2); BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), I.getOperand(0).getReg()) .addReg(DstLo) |
