diff options
author | Hao Liu <Hao.Liu@arm.com> | 2013-10-10 15:01:24 +0000 |
---|---|---|
committer | Hao Liu <Hao.Liu@arm.com> | 2013-10-10 15:01:24 +0000 |
commit | 9123ad8ab9a42d37455dd996568da4a8c27a8d9c (patch) | |
tree | 4b5eee8778bbd9b7c38262deed7477519429c0ef /llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp | |
parent | c319193636480a19a0faf757b851b53d155e7ccd (diff) | |
download | bcm5719-llvm-9123ad8ab9a42d37455dd996568da4a8c27a8d9c.tar.gz bcm5719-llvm-9123ad8ab9a42d37455dd996568da4a8c27a8d9c.zip |
Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).
llvm-svn: 192352
Diffstat (limited to 'llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp')
-rw-r--r-- | llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp index 26bd797e3b3..51335e145b7 100644 --- a/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp +++ b/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp @@ -507,3 +507,33 @@ void AArch64InstPrinter::printNeonUImm64MaskOperand(const MCInst *MI, O << "#0x"; O.write_hex(Mask); } + +// If Count > 1, there are two valid kinds of vector list: +// (1) {Vn.layout, Vn+1.layout, ... , Vm.layout} +// (2) {Vn.layout - Vm.layout} +// We choose the first kind as output. +template <A64Layout::VectorLayout Layout, unsigned Count> +void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { + assert(Count >= 1 && Count <= 4 && "Invalid Number of Vectors"); + + unsigned Reg = MI->getOperand(OpNum).getReg(); + std::string LayoutStr = A64VectorLayoutToString(Layout); + O << "{"; + if (Count > 1) { // Print sub registers separately + bool IsVec64 = (Layout < A64Layout::_16B) ? true : false; + unsigned SubRegIdx = IsVec64 ? AArch64::dsub_0 : AArch64::qsub_0; + for (unsigned I = 0; I < Count; I++) { + std::string Name = getRegisterName(MRI.getSubReg(Reg, SubRegIdx++)); + Name[0] = 'v'; + O << Name << LayoutStr; + if (I != Count - 1) + O << ", "; + } + } else { // Print the register directly when NumVecs is 1. + std::string Name = getRegisterName(Reg); + Name[0] = 'v'; + O << Name << LayoutStr; + } + O << "}"; +} |