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| author | Sander de Smalen <sander.desmalen@arm.com> | 2018-01-03 10:15:46 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2018-01-03 10:15:46 +0000 |
| commit | dc5e081b93f9633d95aef7a3c62fb20170fd262f (patch) | |
| tree | 9456412ffd14ed52d579b1eb1c561e0205773173 /llvm/lib/Target/AArch64/Disassembler | |
| parent | a99154bb126185c6c924d23e43200e75d7a2b736 (diff) | |
| download | bcm5719-llvm-dc5e081b93f9633d95aef7a3c62fb20170fd262f.tar.gz bcm5719-llvm-dc5e081b93f9633d95aef7a3c62fb20170fd262f.zip | |
[AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors.
Summary:
Add a register class for SVE predicate operands that can only be p0-p7 (as opposed to p0-p15)
Patch [1/3] in a series to add predicated ADD/SUB instructions for SVE.
Reviewers: rengolin, mcrosier, evandro, fhahn, echristo, olista01, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Subscribers: aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D41441
llvm-svn: 321699
Diffstat (limited to 'llvm/lib/Target/AArch64/Disassembler')
| -rw-r--r-- | llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index ae278caeda6..30438a159fb 100644 --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -91,6 +91,9 @@ static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decode); +LLVM_ATTRIBUTE_UNUSED static DecodeStatus +DecodePPR_3bRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, + const void *Decode); static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Address, @@ -481,6 +484,16 @@ static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, return Success; } +static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Addr, + const void* Decoder) { + if (RegNo > 7) + return Fail; + + // Just reuse the PPR decode table + return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); +} + static const unsigned VectorDecoderTable[] = { AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, |
