[AArch64] Enable ARMv8.3-A pointer authentication

Add assembler and disassembler support for the ARMv8.3-A pointer
authentication instructions.

Differential Revision: https://reviews.llvm.org/D36517

llvm-svn: 310709

1 files changed, 42 insertions, 0 deletions

diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index e5e80f9c231..4389df7fa53 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -179,6 +179,12 @@ static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
                                                       unsigned RegNo,
                                                       uint64_t Addr,
                                                       const void *Decoder);
+template<int Bits>
+static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
+                               uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeAuthLoadWriteback(llvm::MCInst &Inst, uint32_t insn,
+                                            uint64_t Address,
+                                            const void *Decoder);
 
 static bool Check(DecodeStatus &Out, DecodeStatus In) {
   switch (In) {
@@ -1588,3 +1594,39 @@ static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
                                              AArch64::XSeqPairsClassRegClassID,
                                              RegNo, Addr, Decoder);
 }
+
+template<int Bits>
+static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
+                               uint64_t Address, const void *Decoder) {
+  if (Imm & ~((1LL << Bits) - 1))
+      return Fail;
+
+  // Imm is a signed immediate, so sign extend it.
+  if (Imm & (1 << (Bits - 1)))
+    Imm |= ~((1LL << Bits) - 1);
+
+  Inst.addOperand(MCOperand::createImm(Imm));
+  return Success;
+}
+
+static DecodeStatus DecodeAuthLoadWriteback(llvm::MCInst &Inst, uint32_t insn,
+                                            uint64_t Address,
+                                            const void *Decoder) {
+  unsigned Rt = fieldFromInstruction(insn, 0, 5);
+  unsigned Rn = fieldFromInstruction(insn, 5, 5);
+  unsigned Imm9 = fieldFromInstruction(insn, 12, 9);
+  unsigned S = fieldFromInstruction(insn, 22, 1);
+
+  unsigned Imm = Imm9 | (S << 9);
+
+  // Address writeback
+  DecodeGPR64spRegisterClass(Inst, Rn, Address, Decoder);
+  // Destination
+  DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
+  // Address
+  DecodeGPR64spRegisterClass(Inst, Rn, Address, Decoder);
+  // Offset
+  DecodeSImm<10>(Inst, Imm, Address, Decoder);
+
+  return Success;
+}