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| author | Cullen Rhodes <cullen.rhodes@arm.com> | 2019-06-07 08:37:00 +0000 |
|---|---|---|
| committer | Cullen Rhodes <cullen.rhodes@arm.com> | 2019-06-07 08:37:00 +0000 |
| commit | f7305484841f09dbcacff326730dc3d62addead4 (patch) | |
| tree | 5fdfe0dfd6e9d458e00a14e4202633c71617b67a /llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | |
| parent | 33044a7ae21350954e3523a70f2e4422a4e165ea (diff) | |
| download | bcm5719-llvm-f7305484841f09dbcacff326730dc3d62addead4.tar.gz bcm5719-llvm-f7305484841f09dbcacff326730dc3d62addead4.zip | |
[AArch64][AsmParser] Provide better diagnostics for SVE predicates
Patch by Sander de Smalen (sdesmalen)
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62941
llvm-svn: 362779
Diffstat (limited to 'llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp')
| -rw-r--r-- | llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 891331bb7d9..a51eb24cbb5 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -4470,11 +4470,15 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode, case Match_InvalidSVEPredicateDReg: return Error(Loc, "invalid predicate register."); case Match_InvalidSVEPredicate3bAnyReg: + return Error(Loc, "invalid restricted predicate register, expected p0..p7 (without element suffix)"); case Match_InvalidSVEPredicate3bBReg: + return Error(Loc, "invalid restricted predicate register, expected p0.b..p7.b"); case Match_InvalidSVEPredicate3bHReg: + return Error(Loc, "invalid restricted predicate register, expected p0.h..p7.h"); case Match_InvalidSVEPredicate3bSReg: + return Error(Loc, "invalid restricted predicate register, expected p0.s..p7.s"); case Match_InvalidSVEPredicate3bDReg: - return Error(Loc, "restricted predicate has range [0, 7]."); + return Error(Loc, "invalid restricted predicate register, expected p0.d..p7.d"); case Match_InvalidSVEExactFPImmOperandHalfOne: return Error(Loc, "Invalid floating point constant, expected 0.5 or 1.0."); case Match_InvalidSVEExactFPImmOperandHalfTwo: |
