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| author | Martin Elshuber <martin.elshuber@theobroma-systems.com> | 2018-11-19 14:26:10 +0000 |
|---|---|---|
| committer | Martin Elshuber <martin.elshuber@theobroma-systems.com> | 2018-11-19 14:26:10 +0000 |
| commit | fef3036d3721a9a6a234c54786e3b8bf3d2d0f93 (patch) | |
| tree | b05659f26b00414aa162895dc078bfe6b58bba24 /llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | |
| parent | 0c7460ad057391cae264d405068a70212d770965 (diff) | |
| download | bcm5719-llvm-fef3036d3721a9a6a234c54786e3b8bf3d2d0f93.tar.gz bcm5719-llvm-fef3036d3721a9a6a234c54786e3b8bf3d2d0f93.zip | |
Subject: [PATCH] [CodeGen] Add pass to combine interleaved loads.
This patch defines an interleaved-load-combine pass. The pass searches
for ShuffleVector instructions that represent interleaved loads. Matches are
converted such that they will be captured by the InterleavedAccessPass.
The pass extends LLVMs capabilities to use target specific instruction
selection of interleaved load patterns (e.g.: ld4 on Aarch64
architectures).
Differential Revision: https://reviews.llvm.org/D52653
llvm-svn: 347208
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64TargetMachine.cpp')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index 2f3f87d02b7..6dacbe8a9fe 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -419,8 +419,10 @@ void AArch64PassConfig::addIRPasses() { TargetPassConfig::addIRPasses(); // Match interleaved memory accesses to ldN/stN intrinsics. - if (TM->getOptLevel() != CodeGenOpt::None) + if (TM->getOptLevel() != CodeGenOpt::None) { + addPass(createInterleavedLoadCombinePass()); addPass(createInterleavedAccessPass()); + } if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) { // Call SeparateConstOffsetFromGEP pass to extract constants within indices |
