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author | Tim Northover <tnorthover@apple.com> | 2019-09-09 10:04:23 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2019-09-09 10:04:23 +0000 |
commit | 36147adc0b14b455c6c1d738523f930d0793865c (patch) | |
tree | 756c2b550aee63a34497293ab177ffddb39c035a /llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | |
parent | c11af417e0dd6c04d38bb48f0d77f0b849211ebb (diff) | |
download | bcm5719-llvm-36147adc0b14b455c6c1d738523f930d0793865c.tar.gz bcm5719-llvm-36147adc0b14b455c6c1d738523f930d0793865c.zip |
GlobalISel: add combiner to form indexed loads.
Loosely based on DAGCombiner version, but this part is slightly simpler in
GlobalIsel because all address calculation is performed by G_GEP. That makes
the inc/dec distinction moot so there's just pre/post to think about.
No targets can handle it yet so testing is via a special flag that overrides
target hooks.
llvm-svn: 371384
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64TargetMachine.cpp')
-rw-r--r-- | llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index c3a8ace304a..71928aafa5d 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -504,7 +504,8 @@ bool AArch64PassConfig::addIRTranslator() { } void AArch64PassConfig::addPreLegalizeMachineIR() { - addPass(createAArch64PreLegalizeCombiner()); + bool IsOptNone = getOptLevel() == CodeGenOpt::None; + addPass(createAArch64PreLegalizeCombiner(IsOptNone)); } bool AArch64PassConfig::addLegalizeMachineIR() { |