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authorChad Rosier <mcrosier@codeaurora.org>2013-12-12 15:46:29 +0000
committerChad Rosier <mcrosier@codeaurora.org>2013-12-12 15:46:29 +0000
commit4055f42d22e126ed0c31186e52e5ec08bf030a83 (patch)
tree4d5a97fb6569f80dd26cd364f6cf1b8709eddbcc /llvm/lib/Target/AArch64/AArch64RegisterInfo.td
parent74f444cde58a2ef683a15fae4321342f417f1e13 (diff)
downloadbcm5719-llvm-4055f42d22e126ed0c31186e52e5ec08bf030a83.tar.gz
bcm5719-llvm-4055f42d22e126ed0c31186e52e5ec08bf030a83.zip
[AArch64] Removed unnecessary copy patterns with v1fx types.
- Copy patterns with float/double types are enough. - Fix typos in test case names that were using v1fx. - There is no ACLE intrinsic that uses v1f32 type. And there is no conflict of neon and non-neon ovelapped operations with this type, so there is no need to support operations with this type. - Remove v1f32 from FPR32 register and disallow v1f32 as a legal type for operations. Patch by Ana Pazos! llvm-svn: 197159
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64RegisterInfo.td')
-rw-r--r--llvm/lib/Target/AArch64/AArch64RegisterInfo.td4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index 4e2022c0616..8b1a9cb9074 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -155,7 +155,7 @@ def FPR16 : RegisterClass<"AArch64", [f16, v1i16], 16,
(sequence "H%u", 0, 31)> {
}
-def FPR32 : RegisterClass<"AArch64", [f32, v1i32, v1f32], 32,
+def FPR32 : RegisterClass<"AArch64", [f32, v1i32], 32,
(sequence "S%u", 0, 31)> {
}
@@ -288,4 +288,4 @@ multiclass VectorList_BHSD<string PREFIX, int Count, RegisterClass DRegList,
defm VOne : VectorList_BHSD<"VOne", 1, FPR64, FPR128>;
defm VPair : VectorList_BHSD<"VPair", 2, DPair, QPair>;
defm VTriple : VectorList_BHSD<"VTriple", 3, DTriple, QTriple>;
-defm VQuad : VectorList_BHSD<"VQuad", 4, DQuad, QQuad>; \ No newline at end of file
+defm VQuad : VectorList_BHSD<"VQuad", 4, DQuad, QQuad>;
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