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authorEvandro Menezes <e.menezes@samsung.com>2018-01-30 16:28:01 +0000
committerEvandro Menezes <e.menezes@samsung.com>2018-01-30 16:28:01 +0000
commitf1d01645a76285e53dff50feca1a5791685d946f (patch)
tree54fec9666cf4697a0274855820db511c8bf01bf4 /llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
parentdaaeaba665a45728c799304bd9c4eace7c579d50 (diff)
downloadbcm5719-llvm-f1d01645a76285e53dff50feca1a5791685d946f.tar.gz
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[AArch64] Add new target feature to fuse address generation with load or store
This feature enables the fusion of the address generation and a corresponding load or store together. Differential revision: https://reviews.llvm.org/D42393 llvm-svn: 323782
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64MacroFusion.cpp')
-rw-r--r--llvm/lib/Target/AArch64/AArch64MacroFusion.cpp33
1 files changed, 33 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp b/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
index 6930c816b5a..2f58306f6c6 100644
--- a/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
@@ -150,6 +150,39 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
SecondMI.getOperand(3).getImm() == 48);
}
+ if (ST.hasFuseAddress()) {
+ // Fuse address generation and loads and stores.
+ if ((FirstOpcode == AArch64::INSTRUCTION_LIST_END ||
+ FirstOpcode == AArch64::ADR ||
+ FirstOpcode == AArch64::ADRP) &&
+ ((SecondOpcode == AArch64::STRBBui ||
+ SecondOpcode == AArch64::STRBui ||
+ SecondOpcode == AArch64::STRDui ||
+ SecondOpcode == AArch64::STRHHui ||
+ SecondOpcode == AArch64::STRHui ||
+ SecondOpcode == AArch64::STRQui ||
+ SecondOpcode == AArch64::STRSui ||
+ SecondOpcode == AArch64::STRWui ||
+ SecondOpcode == AArch64::STRXui ||
+ SecondOpcode == AArch64::LDRBBui ||
+ SecondOpcode == AArch64::LDRBui ||
+ SecondOpcode == AArch64::LDRDui ||
+ SecondOpcode == AArch64::LDRHHui ||
+ SecondOpcode == AArch64::LDRHui ||
+ SecondOpcode == AArch64::LDRQui ||
+ SecondOpcode == AArch64::LDRSBWui ||
+ SecondOpcode == AArch64::LDRSBXui ||
+ SecondOpcode == AArch64::LDRSHWui ||
+ SecondOpcode == AArch64::LDRSHXui ||
+ SecondOpcode == AArch64::LDRSWui ||
+ SecondOpcode == AArch64::LDRSui ||
+ SecondOpcode == AArch64::LDRWui ||
+ SecondOpcode == AArch64::LDRXui) &&
+ (FirstOpcode != AArch64::ADR ||
+ SecondMI.getOperand(2).getImm() == 0)))
+ return true;
+ }
+
return false;
}
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