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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-22 03:32:36 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-22 03:32:36 +0000 |
| commit | bfdba5e4fc351d3de15d5536a1d4e04a16573ddf (patch) | |
| tree | 0d1dff23cf739d81409b302850eea4d890fd16b9 /llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | |
| parent | 1eaa04d682d684f7e83c263aa40e78ae8faab378 (diff) | |
| download | bcm5719-llvm-bfdba5e4fc351d3de15d5536a1d4e04a16573ddf.tar.gz bcm5719-llvm-bfdba5e4fc351d3de15d5536a1d4e04a16573ddf.zip | |
IR: Add fp operations to atomicrmw
Add just fadd/fsub for now.
llvm-svn: 351778
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 2530b0af87d..df77e8e7d5b 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -11600,6 +11600,9 @@ AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const { // For the real atomic operations, we have ldxr/stxr up to 128 bits, TargetLowering::AtomicExpansionKind AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const { + if (AI->isFloatingPointOperation()) + return AtomicExpansionKind::CmpXChg; + unsigned Size = AI->getType()->getPrimitiveSizeInBits(); if (Size > 128) return AtomicExpansionKind::None; // Nand not supported in LSE. |
