Revert "[COFF, ARM64] Implement Intrinsic.sponentry for AArch64"

This reverts commit 585b6667b4712e3c7f32401e929855b3313b4ff2.

llvm-svn: 345863

1 files changed, 0 insertions, 12 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index f5652a9f380..3c107016c8b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -2863,8 +2863,6 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
     return LowerFP_EXTEND(Op, DAG);
   case ISD::FRAMEADDR:
     return LowerFRAMEADDR(Op, DAG);
-  case ISD::SPONENTRY:
-    return LowerSPONENTRY(Op, DAG);
   case ISD::RETURNADDR:
     return LowerRETURNADDR(Op, DAG);
   case ISD::INSERT_VECTOR_ELT:
@@ -5173,16 +5171,6 @@ SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
   return FrameAddr;
 }
 
-SDValue AArch64TargetLowering::LowerSPONENTRY(SDValue Op,
-                                              SelectionDAG &DAG) const {
-  MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
-
-  EVT VT = getPointerTy(DAG.getDataLayout());
-  SDLoc DL(Op);
-  int FI = MFI.CreateFixedObject(4, 0, false);
-  return DAG.getFrameIndex(FI, VT);
-}
-
 // FIXME? Maybe this could be a TableGen attribute on some registers and
 // this table could be generated automatically from RegInfo.
 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName, EVT VT,