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author | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2019-02-01 12:26:06 +0000 |
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committer | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2019-02-01 12:26:06 +0000 |
commit | b3ccc5550d985395a7b43cfdd93bc400b332dcdb (patch) | |
tree | acd37f4ea2157bbd8077e13f0627c2b6b3414e9a /llvm/lib/Target/AArch64/AArch64FastISel.cpp | |
parent | f4b19c00b499e26859d0740dec8aecba34e85cbf (diff) | |
download | bcm5719-llvm-b3ccc5550d985395a7b43cfdd93bc400b332dcdb.tar.gz bcm5719-llvm-b3ccc5550d985395a7b43cfdd93bc400b332dcdb.zip |
[AArch64] Optimize floating point materialization
This patch changes isFPImmLegal to return if the value can be enconded
as the immediate operand of a logical instruction besides checking if
for immediate field for fmov.
This optimizes some floating point materization, inclusive values
used on isinf lowering.
Reviewed By: rengolin, efriedma, evandro
Differential Revision: https://reviews.llvm.org/D57044
llvm-svn: 352866
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64FastISel.cpp')
-rw-r--r-- | llvm/lib/Target/AArch64/AArch64FastISel.cpp | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp index a63ef542954..8b033ee6376 100644 --- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp +++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp @@ -405,10 +405,9 @@ unsigned AArch64FastISel::materializeFP(const ConstantFP *CFP, MVT VT) { bool Is64Bit = (VT == MVT::f64); // This checks to see if we can use FMOV instructions to materialize // a constant, otherwise we have to materialize via the constant pool. - if (TLI.isFPImmLegal(Val, VT)) { - int Imm = - Is64Bit ? AArch64_AM::getFP64Imm(Val) : AArch64_AM::getFP32Imm(Val); - assert((Imm != -1) && "Cannot encode floating-point constant."); + int Imm = + Is64Bit ? AArch64_AM::getFP64Imm(Val) : AArch64_AM::getFP32Imm(Val); + if (Imm != -1) { unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi; return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); } |