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authorMatt Arsenault <Matthew.Arsenault@amd.com>2019-06-24 15:50:29 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2019-06-24 15:50:29 +0000
commite3a676e9adba668a7da944766218e98dd4b2c10a (patch)
tree632a983ae9fe72b635cf72262bf2e9a0cbe6dce3 /llvm/lib/Target/AArch64/AArch64CallLowering.h
parent3260ef16bbdecc391d7da8fe3bbe19585f6ccb19 (diff)
downloadbcm5719-llvm-e3a676e9adba668a7da944766218e98dd4b2c10a.tar.gz
bcm5719-llvm-e3a676e9adba668a7da944766218e98dd4b2c10a.zip
CodeGen: Introduce a class for registers
Avoids using a plain unsigned for registers throughoug codegen. Doesn't attempt to change every register use, just something a little more than the set needed to build after changing the return type of MachineOperand::getReg(). llvm-svn: 364191
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64CallLowering.h')
-rw-r--r--llvm/lib/Target/AArch64/AArch64CallLowering.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64CallLowering.h b/llvm/lib/Target/AArch64/AArch64CallLowering.h
index 6aab6bd1703..67a58501fb8 100644
--- a/llvm/lib/Target/AArch64/AArch64CallLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64CallLowering.h
@@ -34,16 +34,16 @@ public:
AArch64CallLowering(const AArch64TargetLowering &TLI);
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
- ArrayRef<unsigned> VRegs,
- unsigned SwiftErrorVReg) const override;
+ ArrayRef<Register> VRegs,
+ Register SwiftErrorVReg) const override;
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
- ArrayRef<unsigned> VRegs) const override;
+ ArrayRef<Register> VRegs) const override;
bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv,
const MachineOperand &Callee, const ArgInfo &OrigRet,
ArrayRef<ArgInfo> OrigArgs,
- unsigned SwiftErrorVReg) const override;
+ Register SwiftErrorVReg) const override;
bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv,
const MachineOperand &Callee, const ArgInfo &OrigRet,
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