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| author | Igor Breger <igor.breger@intel.com> | 2016-08-11 12:13:46 +0000 |
|---|---|---|
| committer | Igor Breger <igor.breger@intel.com> | 2016-08-11 12:13:46 +0000 |
| commit | a77b14d02c9bff204251d67d195df3aaf4fc5299 (patch) | |
| tree | 13fdc376dcadfd94a9b0daff27ed3cea1d541e9d /llvm/lib/TableGen/TGParser.h | |
| parent | 7ca0645c80df06492c65d6b8fc5b28258bb4c4b2 (diff) | |
| download | bcm5719-llvm-a77b14d02c9bff204251d67d195df3aaf4fc5299.tar.gz bcm5719-llvm-a77b14d02c9bff204251d67d195df3aaf4fc5299.zip | |
[AVX512] Fix extractelement i1 lowering.
The previous implementation (not custom) doesn't enforce zeroing off upper bits. The assumption is that i1 PRODUCER (truncate and extractelement) must zero all upper bits, so i1 CONSUMER instructions ( test, zext, save, etc) can be done without additional zeroing.
Make extractelement i1 lowering custom for all vector i1.
Differential Revision: http://reviews.llvm.org/D23246
llvm-svn: 278328
Diffstat (limited to 'llvm/lib/TableGen/TGParser.h')
0 files changed, 0 insertions, 0 deletions
