summaryrefslogtreecommitdiffstats
path: root/llvm/lib/TableGen/TGParser.cpp
diff options
context:
space:
mode:
authorMichael Liao <michael.liao@intel.com>2012-09-06 23:32:48 +0000
committerMichael Liao <michael.liao@intel.com>2012-09-06 23:32:48 +0000
commit026f833368d40969f196680abf888a945d8c5621 (patch)
tree9fcd72e747e0d9339cd94b10688ce0154dc94ef3 /llvm/lib/TableGen/TGParser.cpp
parent4fc47755611f873f5dff814e7ab560f3e3f39c5e (diff)
downloadbcm5719-llvm-026f833368d40969f196680abf888a945d8c5621.tar.gz
bcm5719-llvm-026f833368d40969f196680abf888a945d8c5621.zip
Re-work bit/bits value resolving in tblgen
- This patch is inspired by the failure of the following code snippet which is used to convert enumerable values into encoding bits to improve the readability of td files. class S<int s> { bits<2> V = !if(!eq(s, 8), {0, 0}, !if(!eq(s, 16), {0, 1}, !if(!eq(s, 32), {1, 0}, !if(!eq(s, 64), {1, 1}, {?, ?})))); } Later, PR8330 is found to report not exactly the same bug relevant issue to bit/bits values. - Instead of resolving bit/bits values separately through resolveBitReference(), this patch adds getBit() for all Inits and resolves bit value by resolving plus getting the specified bit. This unifies the resolving of bit with other values and removes redundant logic for resolving bit only. In addition, BitsInit::resolveReferences() is optimized to take advantage of this origanization by resolving VarBitInit's variable reference first and then getting bits from it. - The type interference in '!if' operator is revised to support possible combinations of int and bits/bit in MHS and RHS. - As there may be illegal assignments from integer value to bit, says assign 2 to a bit, but we only check this during instantiation in some cases, e.g. bit V = !if(!eq(x, 17), 0, 2); Verbose diagnostic message is generated when invalid value is resolveed to help locating the error. - PR8330 is fixed as well. llvm-svn: 163360
Diffstat (limited to 'llvm/lib/TableGen/TGParser.cpp')
-rw-r--r--llvm/lib/TableGen/TGParser.cpp41
1 files changed, 17 insertions, 24 deletions
diff --git a/llvm/lib/TableGen/TGParser.cpp b/llvm/lib/TableGen/TGParser.cpp
index 5e2b66ed69d..aee93e7696b 100644
--- a/llvm/lib/TableGen/TGParser.cpp
+++ b/llvm/lib/TableGen/TGParser.cpp
@@ -1044,35 +1044,28 @@ Init *TGParser::ParseOperation(Record *CurRec) {
switch (LexCode) {
default: llvm_unreachable("Unhandled code!");
case tgtok::XIf: {
- // FIXME: The `!if' operator doesn't handle non-TypedInit well at
- // all. This can be made much more robust.
- TypedInit *MHSt = dynamic_cast<TypedInit*>(MHS);
- TypedInit *RHSt = dynamic_cast<TypedInit*>(RHS);
-
RecTy *MHSTy = 0;
RecTy *RHSTy = 0;
- if (MHSt == 0 && RHSt == 0) {
- BitsInit *MHSbits = dynamic_cast<BitsInit*>(MHS);
- BitsInit *RHSbits = dynamic_cast<BitsInit*>(RHS);
-
- if (MHSbits && RHSbits &&
- MHSbits->getNumBits() == RHSbits->getNumBits()) {
- Type = BitRecTy::get();
- break;
- } else {
- BitInit *MHSbit = dynamic_cast<BitInit*>(MHS);
- BitInit *RHSbit = dynamic_cast<BitInit*>(RHS);
-
- if (MHSbit && RHSbit) {
- Type = BitRecTy::get();
- break;
- }
- }
- } else if (MHSt != 0 && RHSt != 0) {
+ if (TypedInit *MHSt = dynamic_cast<TypedInit*>(MHS))
MHSTy = MHSt->getType();
+ if (BitsInit *MHSbits = dynamic_cast<BitsInit*>(MHS))
+ MHSTy = BitsRecTy::get(MHSbits->getNumBits());
+ if (dynamic_cast<BitInit*>(MHS))
+ MHSTy = BitRecTy::get();
+
+ if (TypedInit *RHSt = dynamic_cast<TypedInit*>(RHS))
RHSTy = RHSt->getType();
- }
+ if (BitsInit *RHSbits = dynamic_cast<BitsInit*>(RHS))
+ RHSTy = BitsRecTy::get(RHSbits->getNumBits());
+ if (dynamic_cast<BitInit*>(RHS))
+ RHSTy = BitRecTy::get();
+
+ // For UnsetInit, it's typed from the other hand.
+ if (dynamic_cast<UnsetInit*>(MHS))
+ MHSTy = RHSTy;
+ if (dynamic_cast<UnsetInit*>(RHS))
+ RHSTy = MHSTy;
if (!MHSTy || !RHSTy) {
TokError("could not get type for !if");
OpenPOWER on IntegriCloud