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| author | Yichao Yu <yyc1992@gmail.com> | 2016-12-15 22:36:53 +0000 |
|---|---|---|
| committer | Yichao Yu <yyc1992@gmail.com> | 2016-12-15 22:36:53 +0000 |
| commit | 8f8cdd00dab0c56011806eb0e2fe211364be71f7 (patch) | |
| tree | f197159d279cb6e101c314f089b5f418e6eeac06 /llvm/lib/TableGen/SetTheory.cpp | |
| parent | d69b9414b3cbd2ba738e7d48159643c69633c4d2 (diff) | |
| download | bcm5719-llvm-8f8cdd00dab0c56011806eb0e2fe211364be71f7.tar.gz bcm5719-llvm-8f8cdd00dab0c56011806eb0e2fe211364be71f7.zip | |
Fix R_AARCH64_MOVW_UABS_G3 relocation
Summary: The relocation is missing mask so an address that has non-zero bits in 47:43 may overwrite the register number. (Frequently shows up as target register changed to `xzr`....)
Reviewers: t.p.northover, lhames
Subscribers: davide, aemerson, rengolin, llvm-commits
Differential Revision: https://reviews.llvm.org/D27609
llvm-svn: 289880
Diffstat (limited to 'llvm/lib/TableGen/SetTheory.cpp')
0 files changed, 0 insertions, 0 deletions
