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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-29 01:13:47 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-29 01:13:47 +0000 |
| commit | 216d8ff60b51ce112eab9c887cc5a82895fc69e1 (patch) | |
| tree | 2206c11fe31b6b3255572bb41ed726bbeb0232c2 /llvm/lib/Support/regexec.c | |
| parent | 8ec5c1004265f5da323dfc3b2fe929c0557804c8 (diff) | |
| download | bcm5719-llvm-216d8ff60b51ce112eab9c887cc5a82895fc69e1.tar.gz bcm5719-llvm-216d8ff60b51ce112eab9c887cc5a82895fc69e1.zip | |
AMDGPU: Don't use frame virtual registers
SGPR spills aren't really handled after SILowerSGPRSpills. In order to
directly control what happens if the scavenger needs to spill, the
scavenger needs to be used directly. There is an alternative to
spilling in these contexts anyway since the frame register can be
increment and restored.
This does present another possible issue if spilling is needed for the
unused carry out if an add is needed. I think this can be avoided by
using a scalar add (although that clobbers SCC, which happens anyway).
llvm-svn: 370281
Diffstat (limited to 'llvm/lib/Support/regexec.c')
0 files changed, 0 insertions, 0 deletions
