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| author | Chris Dewhurst <chris.dewhurst@lero.ie> | 2016-04-22 08:17:17 +0000 |
|---|---|---|
| committer | Chris Dewhurst <chris.dewhurst@lero.ie> | 2016-04-22 08:17:17 +0000 |
| commit | 601970296070d04b19aae5cf665b9cde0d55ef08 (patch) | |
| tree | 90690e528b1f86f3722437cfcd450cfe9583d647 /llvm/lib/Support/raw_os_ostream.cpp | |
| parent | 431fc8af7bece9bfc733227218254b3d64d8a0f6 (diff) | |
| download | bcm5719-llvm-601970296070d04b19aae5cf665b9cde0d55ef08.tar.gz bcm5719-llvm-601970296070d04b19aae5cf665b9cde0d55ef08.zip | |
[Sparc] This provides support for itineraries on Sparc.
Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future.
The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this.
As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary.
Phabricator Review: http://reviews.llvm.org/D19359
llvm-svn: 267121
Diffstat (limited to 'llvm/lib/Support/raw_os_ostream.cpp')
0 files changed, 0 insertions, 0 deletions
