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author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-12 11:55:58 +0000 |
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committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-12 11:55:58 +0000 |
commit | 1f6f0f4b54c4fcb1b0e224434f066f2e62def8e9 (patch) | |
tree | ab762aada13fec86ef3f01584158d9bb09d6c04d /llvm/lib/Support/YAMLTraits.cpp | |
parent | 28a0ca0759071a0e4e5ebac8bbcde0f765bd2957 (diff) | |
download | bcm5719-llvm-1f6f0f4b54c4fcb1b0e224434f066f2e62def8e9.tar.gz bcm5719-llvm-1f6f0f4b54c4fcb1b0e224434f066f2e62def8e9.zip |
[mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64
Summary:
To make this work for both AFGR64 and FGR64 register sets, I've had to make the
instruction definition consistent with the white lie (that it reads the lower
32-bits of the register) when they are generated by expandBuildPairF64().
Corrected the definition of hasMips32r2() and hasMips64r2() to include
MIPS32r6 and MIPS64r6.
Depends on D3956
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3957
llvm-svn: 210771
Diffstat (limited to 'llvm/lib/Support/YAMLTraits.cpp')
0 files changed, 0 insertions, 0 deletions