diff options
| author | Luo, Yuanke <yuanke.luo@intel.com> | 2019-05-06 08:22:37 +0000 |
|---|---|---|
| committer | Luo, Yuanke <yuanke.luo@intel.com> | 2019-05-06 08:22:37 +0000 |
| commit | beec41c656e7d716fd5755cce12e4934fdced267 (patch) | |
| tree | cbb53258bcd3f11adc2ee6a8467def1692b30623 /llvm/lib/Support/Host.cpp | |
| parent | fb607580046ed9fe2891151a23375f0c524d29b3 (diff) | |
| download | bcm5719-llvm-beec41c656e7d716fd5755cce12e4934fdced267.tar.gz bcm5719-llvm-beec41c656e7d716fd5755cce12e4934fdced267.zip | |
Enable AVX512_BF16 instructions, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
VCVTNE2PS2BF16: Convert Two Packed Single Data to One Packed BF16 Data.
VCVTNEPS2BF16: Convert Packed Single Data to Packed BF16 Data.
VDPBF16PS: Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
For more details about BF16 isa, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Author: LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, RKSimon, spatel
Reviewed By: craig.topper
Subscribers: kristina, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60550
llvm-svn: 360017
Diffstat (limited to 'llvm/lib/Support/Host.cpp')
| -rw-r--r-- | llvm/lib/Support/Host.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Support/Host.cpp b/llvm/lib/Support/Host.cpp index 69362704687..4a7eff3f6e3 100644 --- a/llvm/lib/Support/Host.cpp +++ b/llvm/lib/Support/Host.cpp @@ -1375,6 +1375,9 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) { // detecting features using the "-march=native" flag. // For more info, see X86 ISA docs. Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); + bool HasLeaf7Subleaf1 = + MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); + Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; bool HasLeafD = MaxLevel >= 0xd && !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); |
