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authorMatt Arsenault <Matthew.Arsenault@amd.com>2014-11-02 23:46:51 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2014-11-02 23:46:51 +0000
commiteb49216bba6a8d00a67817951f98f85b43a8bbbf (patch)
tree9c7889f61f81caed1af33a890355bdc16b1c851e /llvm/lib/ProfileData/SampleProfReader.cpp
parent3c0714a3eae0a121d5fede3d0847338b1f9b3494 (diff)
downloadbcm5719-llvm-eb49216bba6a8d00a67817951f98f85b43a8bbbf.tar.gz
bcm5719-llvm-eb49216bba6a8d00a67817951f98f85b43a8bbbf.zip
Support REG_SEQUENCE in tablegen.
The problem is mostly that variadic output instruction aren't handled, so it is rejected for having an inconsistent number of operands, and then the right number of operands isn't emitted. llvm-svn: 221117
Diffstat (limited to 'llvm/lib/ProfileData/SampleProfReader.cpp')
0 files changed, 0 insertions, 0 deletions
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