diff options
| author | Prakhar Bahuguna <prakhar.bahuguna@arm.com> | 2016-12-15 07:59:08 +0000 |
|---|---|---|
| committer | Prakhar Bahuguna <prakhar.bahuguna@arm.com> | 2016-12-15 07:59:08 +0000 |
| commit | 52a7dd7d7825b269ae569db0e2bcb193c7698666 (patch) | |
| tree | 7957bd2c8f0c07fbbcfdc331ca848a051dab6613 /llvm/lib/ObjectYAML | |
| parent | 342beeb91eb03ce92e598d593325c8475673768e (diff) | |
| download | bcm5719-llvm-52a7dd7d7825b269ae569db0e2bcb193c7698666.tar.gz bcm5719-llvm-52a7dd7d7825b269ae569db0e2bcb193c7698666.zip | |
[ARM] Implement execute-only support in CodeGen
This implements execute-only support for ARM code generation, which
prevents the compiler from generating data accesses to code sections.
The following changes are involved:
* Add the CodeGen option "-arm-execute-only" to the ARM code generator.
* Add the clang flag "-mexecute-only" as well as the GCC-compatible
alias "-mpure-code" to enable this option.
* When enabled, literal pools are replaced with MOVW/MOVT instructions,
with VMOV used in addition for floating-point literals. As the MOVT
instruction is required, execute-only support is only available in
Thumb mode for targets supporting ARMv8-M baseline or Thumb2.
* Jump tables are placed in data sections when in execute-only mode.
* The execute-only text section is assigned section ID 0, and is
marked as unreadable with the SHF_ARM_PURECODE flag with symbol 'y'.
This also overrides selection of ELF sections for globals.
llvm-svn: 289784
Diffstat (limited to 'llvm/lib/ObjectYAML')
| -rw-r--r-- | llvm/lib/ObjectYAML/ELFYAML.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/ObjectYAML/ELFYAML.cpp b/llvm/lib/ObjectYAML/ELFYAML.cpp index 0c42a1ad2fb..fe9af9f3ac7 100644 --- a/llvm/lib/ObjectYAML/ELFYAML.cpp +++ b/llvm/lib/ObjectYAML/ELFYAML.cpp @@ -423,6 +423,9 @@ void ScalarBitSetTraits<ELFYAML::ELF_SHF>::bitset(IO &IO, BCase(SHF_GROUP) BCase(SHF_TLS) switch(Object->Header.Machine) { + case ELF::EM_ARM: + BCase(SHF_ARM_PURECODE) + break; case ELF::EM_AMDGPU: BCase(SHF_AMDGPU_HSA_GLOBAL) BCase(SHF_AMDGPU_HSA_READONLY) |
