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| author | Hal Finkel <hfinkel@anl.gov> | 2013-08-03 12:25:10 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-08-03 12:25:10 +0000 |
| commit | b176acb6b72e12f301e0ea9c9e8664f5ba6de610 (patch) | |
| tree | 3f74abac9d13d1505444769572a5943fa71882f5 /llvm/lib/Object | |
| parent | 2f9cce2cd6715bceeab0ec052e115ce64252fb88 (diff) | |
| download | bcm5719-llvm-b176acb6b72e12f301e0ea9c9e8664f5ba6de610.tar.gz bcm5719-llvm-b176acb6b72e12f301e0ea9c9e8664f5ba6de610.zip | |
Fix PPC64 64-bit GPR inline asm constraint matching
Internally, the PowerPC backend names the 32-bit GPRs R[0-9]+, and names the
64-bit parent GPRs X[0-9]+. When matching inline assembly constraints with
explicit register names, on PPC64 when an i64 MVT has been requested, we need
to follow gcc's convention of using r[0-9]+ to refer to the 64-bit (parent)
registers.
At some point, we'll probably want to arrange things so that the generic code
in TargetLowering uses the AsmName fields declared in *RegisterInfo.td in order
to match these inline asm register constraints. If we do that, this change can
be reverted.
llvm-svn: 187693
Diffstat (limited to 'llvm/lib/Object')
0 files changed, 0 insertions, 0 deletions
