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| author | Sanjay Patel <spatel@rotateright.com> | 2019-09-02 14:52:09 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2019-09-02 14:52:09 +0000 |
| commit | 4e54cf3e0e71b38b2fde1a815e8460b14026762a (patch) | |
| tree | d0a15d43d773e1a3eee0234e48b23ad8ca378fed /llvm/lib/Object/ObjectFile.cpp | |
| parent | 6e18266aa4dd78953557b8614cb9ff260bad7c65 (diff) | |
| download | bcm5719-llvm-4e54cf3e0e71b38b2fde1a815e8460b14026762a.tar.gz bcm5719-llvm-4e54cf3e0e71b38b2fde1a815e8460b14026762a.zip | |
[DAGCombiner] try to form test+set out of shift+mask patterns
The motivating bugs are:
https://bugs.llvm.org/show_bug.cgi?id=41340
https://bugs.llvm.org/show_bug.cgi?id=42697
As discussed there, we could view this as a failure of IR canonicalization,
but then we would need to implement a backend fixup with target overrides
to get this right in all cases. Instead, we can just view this as a codegen
opportunity. It's not even clear for x86 exactly when we should favor
test+set; some CPUs have better theoretical throughput for the ALU ops than
bt/test.
This patch is made more complicated than I expected because there's an early
DAGCombine for 'and' that can change types of the intermediate ops via
trunc+anyext.
Differential Revision: https://reviews.llvm.org/D66687
llvm-svn: 370668
Diffstat (limited to 'llvm/lib/Object/ObjectFile.cpp')
0 files changed, 0 insertions, 0 deletions
