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| author | Ashutosh Nema <ashu1212@gmail.com> | 2016-05-18 11:56:23 +0000 |
|---|---|---|
| committer | Ashutosh Nema <ashu1212@gmail.com> | 2016-05-18 11:56:23 +0000 |
| commit | 51c9dd0081a677204de63decaa7c58e276c364e7 (patch) | |
| tree | ea30268f1698578515e2fa77759e1aa8922c76e1 /llvm/lib/Object/IRObjectFile.cpp | |
| parent | 47ea5424d2d6c134bd21bfdf6f8d9b6197022805 (diff) | |
| download | bcm5719-llvm-51c9dd0081a677204de63decaa7c58e276c364e7.tar.gz bcm5719-llvm-51c9dd0081a677204de63decaa7c58e276c364e7.zip | |
Add new intrinsic support for MONITORX and MWAITX instructions
Summary:
MONITORX/MWAITX instructions provide similar capability to the MONITOR/MWAIT
pair while adding a timer function, such that another termination of the MWAITX
instruction occurs when the timer expires. The presence of the MONITORX and
MWAITX instructions is indicated by CPUID 8000_0001, ECX, bit 29.
The MONITORX and MWAITX instructions are intercepted by the same bits that
intercept MONITOR and MWAIT. MONITORX instruction establishes a range to be
monitored. MWAITX instruction causes the processor to stop instruction
execution and enter an implementation-dependent optimized state until
occurrence of a class of events.
Opcode of MONITORX instruction is "0F 01 FA". Opcode of MWAITX instruction is
"0F 01 FB". These opcode information is used in adding tests for the
disassembler.
These instructions are enabled for AMD's bdver4 architecture.
Patch by Ganesh Gopalasubramanian!
Reviewers: echristo, craig.topper
Subscribers: RKSimon, joker.eph, llvm-commits, cfe-commits
Differential Revision: http://reviews.llvm.org/D19796
llvm-svn: 269907
Diffstat (limited to 'llvm/lib/Object/IRObjectFile.cpp')
0 files changed, 0 insertions, 0 deletions
