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author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2019-04-27 11:59:11 +0000 |
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committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2019-04-27 11:59:11 +0000 |
commit | d77dc9ada20655977d1f43494d686ed7f403f030 (patch) | |
tree | d51453ea2a22e30da0a170847470faf53ded576d /llvm/lib/MCA | |
parent | b82144b6e4b535fe266b0d970def849f84ff9137 (diff) | |
download | bcm5719-llvm-d77dc9ada20655977d1f43494d686ed7f403f030.tar.gz bcm5719-llvm-d77dc9ada20655977d1f43494d686ed7f403f030.zip |
[MCA] Add field `IsEliminated` to class Instruction. NFCI
llvm-svn: 359377
Diffstat (limited to 'llvm/lib/MCA')
-rw-r--r-- | llvm/lib/MCA/Stages/DispatchStage.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/MCA/Stages/DispatchStage.cpp b/llvm/lib/MCA/Stages/DispatchStage.cpp index b55ac70307a..80d6da09b5e 100644 --- a/llvm/lib/MCA/Stages/DispatchStage.cpp +++ b/llvm/lib/MCA/Stages/DispatchStage.cpp @@ -95,11 +95,11 @@ Error DispatchStage::dispatch(InstRef IR) { AvailableEntries = 0; // Check if this is an optimizable reg-reg move. - bool IsEliminated = false; if (IS.isOptimizableMove()) { assert(IS.getDefs().size() == 1 && "Expected a single input!"); assert(IS.getUses().size() == 1 && "Expected a single output!"); - IsEliminated = PRF.tryEliminateMove(IS.getDefs()[0], IS.getUses()[0]); + if (PRF.tryEliminateMove(IS.getDefs()[0], IS.getUses()[0])) + IS.setEliminated(); } if (IS.isMemOp()) @@ -114,7 +114,7 @@ Error DispatchStage::dispatch(InstRef IR) { // // We also don't update data dependencies for instructions that have been // eliminated at register renaming stage. - if (!IsEliminated) { + if (!IS.isEliminated()) { for (ReadState &RS : IS.getUses()) PRF.addRegisterRead(RS, STI); } |