[MCA] Slightly refactor method writeStartEvent in WriteState and ReadState. NFCI

This is another change in preparation for PR37494.
No functional change intended.

llvm-svn: 354261

3 files changed, 13 insertions, 13 deletions

diff --git a/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp b/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp
index 3621d182b3e..995c50fc6a8 100644
--- a/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp
+++ b/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp
@@ -188,7 +188,7 @@ void RegisterFile::addRegisterWrite(WriteRef Write,
       if (OtherWS && (OtherWrite.getSourceIndex() != Write.getSourceIndex())) {
         // This partial write has a false dependency on RenameAs.
         assert(!IsEliminated && "Unexpected partial update!");
-        OtherWS->addUser(&WS);
+        OtherWS->addUser(OtherWrite.getSourceIndex(), &WS);
       }
     }
   }
@@ -425,7 +425,7 @@ void RegisterFile::addRegisterRead(ReadState &RS,
     WriteState &WS = *WR.getWriteState();
     unsigned WriteResID = WS.getWriteResourceID();
     int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID);
-    WS.addUser(&RS, ReadAdvance);
+    WS.addUser(WR.getSourceIndex(), &RS, ReadAdvance);
   }
 }
 
diff --git a/llvm/lib/MCA/HardwareUnits/Scheduler.cpp b/llvm/lib/MCA/HardwareUnits/Scheduler.cpp
index b5f3617b08f..33db5d24f64 100644
--- a/llvm/lib/MCA/HardwareUnits/Scheduler.cpp
+++ b/llvm/lib/MCA/HardwareUnits/Scheduler.cpp
@@ -74,7 +74,7 @@ void Scheduler::issueInstructionImpl(
 
   // Notify the instruction that it started executing.
   // This updates the internal state of each write.
-  IS->execute();
+  IS->execute(IR.getSourceIndex());
 
   if (IS->isExecuting())
     IssuedSet.emplace_back(IR);
diff --git a/llvm/lib/MCA/Instruction.cpp b/llvm/lib/MCA/Instruction.cpp
index b1508a0ade0..58f02503137 100644
--- a/llvm/lib/MCA/Instruction.cpp
+++ b/llvm/lib/MCA/Instruction.cpp
@@ -18,7 +18,7 @@
 namespace llvm {
 namespace mca {
 
-void ReadState::writeStartEvent(unsigned Cycles) {
+void ReadState::writeStartEvent(unsigned IID, unsigned RegID, unsigned Cycles) {
   assert(DependentWrites);
   assert(CyclesLeft == UNKNOWN_CYCLES);
 
@@ -36,7 +36,7 @@ void ReadState::writeStartEvent(unsigned Cycles) {
   }
 }
 
-void WriteState::onInstructionIssued() {
+void WriteState::onInstructionIssued(unsigned IID) {
   assert(CyclesLeft == UNKNOWN_CYCLES);
   // Update the number of cycles left based on the WriteDescriptor info.
   CyclesLeft = getLatency();
@@ -46,30 +46,30 @@ void WriteState::onInstructionIssued() {
   for (const std::pair<ReadState *, int> &User : Users) {
     ReadState *RS = User.first;
     unsigned ReadCycles = std::max(0, CyclesLeft - User.second);
-    RS->writeStartEvent(ReadCycles);
+    RS->writeStartEvent(IID, RegisterID, ReadCycles);
   }
 
   // Notify any writes that are in a false dependency with this write.
   if (PartialWrite)
-    PartialWrite->writeStartEvent(CyclesLeft);
+    PartialWrite->writeStartEvent(IID, RegisterID, CyclesLeft);
 }
 
-void WriteState::addUser(ReadState *User, int ReadAdvance) {
+void WriteState::addUser(unsigned IID, ReadState *User, int ReadAdvance) {
   // If CyclesLeft is different than -1, then we don't need to
   // update the list of users. We can just notify the user with
   // the actual number of cycles left (which may be zero).
   if (CyclesLeft != UNKNOWN_CYCLES) {
     unsigned ReadCycles = std::max(0, CyclesLeft - ReadAdvance);
-    User->writeStartEvent(ReadCycles);
+    User->writeStartEvent(IID, RegisterID, ReadCycles);
     return;
   }
 
   Users.emplace_back(User, ReadAdvance);
 }
 
-void WriteState::addUser(WriteState *User) {
+void WriteState::addUser(unsigned IID, WriteState *User) {
   if (CyclesLeft != UNKNOWN_CYCLES) {
-    User->writeStartEvent(std::max(0, CyclesLeft));
+    User->writeStartEvent(IID, RegisterID, std::max(0, CyclesLeft));
     return;
   }
 
@@ -131,7 +131,7 @@ void Instruction::dispatch(unsigned RCUToken) {
     updatePending();
 }
 
-void Instruction::execute() {
+void Instruction::execute(unsigned IID) {
   assert(Stage == IS_READY);
   Stage = IS_EXECUTING;
 
@@ -139,7 +139,7 @@ void Instruction::execute() {
   CyclesLeft = getLatency();
 
   for (WriteState &WS : getDefs())
-    WS.onInstructionIssued();
+    WS.onInstructionIssued(IID);
 
   // Transition to the "executed" stage if this is a zero-latency instruction.
   if (!CyclesLeft)