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author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2019-02-15 18:05:59 +0000 |
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committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2019-02-15 18:05:59 +0000 |
commit | 5ad52e35a8e40aacb77cdb59c10f1b19c6ca1ee2 (patch) | |
tree | 5e293b774819f147901da5d30fbdd61e50f3f069 /llvm/lib/MCA | |
parent | da0487f3f26f9514d43806845d6fbc80f3af85cc (diff) | |
download | bcm5719-llvm-5ad52e35a8e40aacb77cdb59c10f1b19c6ca1ee2.tar.gz bcm5719-llvm-5ad52e35a8e40aacb77cdb59c10f1b19c6ca1ee2.zip |
[MCA][LSUnit] Return the ID of the dependent memory operation from method
isReady(). NFCI
This is yet another change in preparation for a fix for PR37494.
llvm-svn: 354150
Diffstat (limited to 'llvm/lib/MCA')
-rw-r--r-- | llvm/lib/MCA/HardwareUnits/LSUnit.cpp | 25 | ||||
-rw-r--r-- | llvm/lib/MCA/HardwareUnits/Scheduler.cpp | 3 |
2 files changed, 16 insertions, 12 deletions
diff --git a/llvm/lib/MCA/HardwareUnits/LSUnit.cpp b/llvm/lib/MCA/HardwareUnits/LSUnit.cpp index 2adc20f8255..4f49fbd2bb4 100644 --- a/llvm/lib/MCA/HardwareUnits/LSUnit.cpp +++ b/llvm/lib/MCA/HardwareUnits/LSUnit.cpp @@ -93,7 +93,7 @@ LSUnit::Status LSUnit::isAvailable(const InstRef &IR) const { return LSUnit::LSU_AVAILABLE; } -bool LSUnit::isReady(const InstRef &IR) const { +unsigned LSUnit::isReady(const InstRef &IR) const { const InstrDesc &Desc = IR.getInstruction()->getDesc(); const unsigned Index = IR.getSourceIndex(); bool IsALoad = Desc.MayLoad; @@ -106,49 +106,52 @@ bool LSUnit::isReady(const InstRef &IR) const { unsigned LoadBarrierIndex = *LoadBarriers.begin(); // A younger load cannot pass a older load barrier. if (Index > LoadBarrierIndex) - return false; + return LoadBarrierIndex; // A load barrier cannot pass a older load. if (Index == LoadBarrierIndex && Index != *LoadQueue.begin()) - return false; + return *LoadQueue.begin(); } if (IsAStore && !StoreBarriers.empty()) { unsigned StoreBarrierIndex = *StoreBarriers.begin(); // A younger store cannot pass a older store barrier. if (Index > StoreBarrierIndex) - return false; + return StoreBarrierIndex; // A store barrier cannot pass a older store. if (Index == StoreBarrierIndex && Index != *StoreQueue.begin()) - return false; + return *StoreQueue.begin(); } // A load may not pass a previous store unless flag 'NoAlias' is set. // A load may pass a previous load. if (NoAlias && IsALoad) - return true; + return Index; if (StoreQueue.size()) { // A load may not pass a previous store. // A store may not pass a previous store. if (Index > *StoreQueue.begin()) - return false; + return *StoreQueue.begin(); } // Okay, we are older than the oldest store in the queue. // If there are no pending loads, then we can say for sure that this // instruction is ready. if (isLQEmpty()) - return true; + return Index; // Check if there are no older loads. if (Index <= *LoadQueue.begin()) - return true; + return Index; // There is at least one younger load. // - // A store may not pass a previous load. // A load may pass a previous load. - return !IsAStore; + if (IsALoad) + return Index; + + // A store may not pass a previous load. + return *LoadQueue.begin(); } void LSUnit::onInstructionExecuted(const InstRef &IR) { diff --git a/llvm/lib/MCA/HardwareUnits/Scheduler.cpp b/llvm/lib/MCA/HardwareUnits/Scheduler.cpp index a7a6ed9570f..b5f3617b08f 100644 --- a/llvm/lib/MCA/HardwareUnits/Scheduler.cpp +++ b/llvm/lib/MCA/HardwareUnits/Scheduler.cpp @@ -288,7 +288,8 @@ void Scheduler::dispatch(const InstRef &IR) { bool Scheduler::isReady(const InstRef &IR) const { const InstrDesc &Desc = IR.getInstruction()->getDesc(); bool IsMemOp = Desc.MayLoad || Desc.MayStore; - return IR.getInstruction()->isReady() && (!IsMemOp || LSU.isReady(IR)); + return IR.getInstruction()->isReady() && + (!IsMemOp || LSU.isReady(IR) == IR.getSourceIndex()); } } // namespace mca |