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authorAndrew Trick <atrick@apple.com>2012-09-17 23:00:42 +0000
committerAndrew Trick <atrick@apple.com>2012-09-17 23:00:42 +0000
commit8e7f202e32149f86bb15813398cc8f3b92b12387 (patch)
treef7a9c576229d0f8dfc51d9fbbbd548e2849078e6 /llvm/lib/MC/MCSubtargetInfo.cpp
parent2b006e42319903437a3b2231b8c99eca5d940946 (diff)
downloadbcm5719-llvm-8e7f202e32149f86bb15813398cc8f3b92b12387.tar.gz
bcm5719-llvm-8e7f202e32149f86bb15813398cc8f3b92b12387.zip
Revert r164061-r164067. Most of the new subtarget emitter.
I have to work out the Target/CodeGen header dependencies before putting this back. llvm-svn: 164072
Diffstat (limited to 'llvm/lib/MC/MCSubtargetInfo.cpp')
-rw-r--r--llvm/lib/MC/MCSubtargetInfo.cpp37
1 files changed, 14 insertions, 23 deletions
diff --git a/llvm/lib/MC/MCSubtargetInfo.cpp b/llvm/lib/MC/MCSubtargetInfo.cpp
index 3eae8cef1e1..47735a492de 100644
--- a/llvm/lib/MC/MCSubtargetInfo.cpp
+++ b/llvm/lib/MC/MCSubtargetInfo.cpp
@@ -19,28 +19,11 @@ using namespace llvm;
MCSchedModel MCSchedModel::DefaultSchedModel; // For unknown processors.
-/// ReInitMCSubtargetInfo - Set or chaing the CPU (optionally supplemented
-/// with feature string). Recompute feature bits and scheduling model.
-void
-MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
- SubtargetFeatures Features(FS);
- FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
- ProcFeatures, NumFeatures);
-
- if (!CPU.empty())
- CPUSchedModel = getSchedModelForCPU(CPU);
- else
- CPUSchedModel = &MCSchedModel::DefaultSchedModel;
-}
-
void
MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
const SubtargetFeatureKV *PF,
const SubtargetFeatureKV *PD,
const SubtargetInfoKV *ProcSched,
- const MCWriteProcResEntry *WPR,
- const MCWriteLatencyEntry *WL,
- const MCReadAdvanceEntry *RA,
const InstrStage *IS,
const unsigned *OC,
const unsigned *FP,
@@ -49,17 +32,25 @@ MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
ProcFeatures = PF;
ProcDesc = PD;
ProcSchedModels = ProcSched;
- WriteProcResTable = WPR;
- WriteLatencyTable = WL;
- ReadAdvanceTable = RA;
-
Stages = IS;
OperandCycles = OC;
ForwardingPaths = FP;
NumFeatures = NF;
NumProcs = NP;
- InitMCProcessorInfo(CPU, FS);
+ SubtargetFeatures Features(FS);
+ FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
+ ProcFeatures, NumFeatures);
+}
+
+
+/// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with
+/// feature string) and recompute feature bits.
+uint64_t MCSubtargetInfo::ReInitMCSubtargetInfo(StringRef CPU, StringRef FS) {
+ SubtargetFeatures Features(FS);
+ FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
+ ProcFeatures, NumFeatures);
+ return FeatureBits;
}
/// ToggleFeature - Toggle a feature and returns the re-computed feature
@@ -114,5 +105,5 @@ MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
/// Initialize an InstrItineraryData instance.
void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
InstrItins =
- InstrItineraryData(CPUSchedModel, Stages, OperandCycles, ForwardingPaths);
+ InstrItineraryData(0, Stages, OperandCycles, ForwardingPaths);
}
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