diff options
author | Andrew Trick <atrick@apple.com> | 2012-09-17 22:18:55 +0000 |
---|---|---|
committer | Andrew Trick <atrick@apple.com> | 2012-09-17 22:18:55 +0000 |
commit | 0923f8183bdc38db0c42a5c11544852e8f695ddd (patch) | |
tree | 115e48c38bd3e890238768c2871a6f3dd786801e /llvm/lib/MC/MCSubtargetInfo.cpp | |
parent | a72fca6becc93f9b954c604e277e1c571d4316e6 (diff) | |
download | bcm5719-llvm-0923f8183bdc38db0c42a5c11544852e8f695ddd.tar.gz bcm5719-llvm-0923f8183bdc38db0c42a5c11544852e8f695ddd.zip |
TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.
llvm-svn: 164061
Diffstat (limited to 'llvm/lib/MC/MCSubtargetInfo.cpp')
-rw-r--r-- | llvm/lib/MC/MCSubtargetInfo.cpp | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/llvm/lib/MC/MCSubtargetInfo.cpp b/llvm/lib/MC/MCSubtargetInfo.cpp index 47735a492de..34b7eeabbc8 100644 --- a/llvm/lib/MC/MCSubtargetInfo.cpp +++ b/llvm/lib/MC/MCSubtargetInfo.cpp @@ -24,6 +24,9 @@ MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, const SubtargetFeatureKV *PF, const SubtargetFeatureKV *PD, const SubtargetInfoKV *ProcSched, + const MCWriteProcResEntry *WPR, + const MCWriteLatencyEntry *WL, + const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP, @@ -32,6 +35,10 @@ MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, ProcFeatures = PF; ProcDesc = PD; ProcSchedModels = ProcSched; + WriteProcResTable = WPR; + WriteLatencyTable = WL; + ReadAdvanceTable = RA; + Stages = IS; OperandCycles = OC; ForwardingPaths = FP; @@ -41,8 +48,9 @@ MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, SubtargetFeatures Features(FS); FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs, ProcFeatures, NumFeatures); -} + CPUSchedModel = getSchedModelForCPU(CPU); +} /// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with /// feature string) and recompute feature bits. |