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| author | Bob Wilson <bob.wilson@apple.com> | 2010-12-09 18:58:31 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-12-09 18:58:31 +0000 |
| commit | d6a7301c78efdf8193af9ccbc68c0b43ec03908c (patch) | |
| tree | ff0f991373c67c79dbddf92280e333d68082dcda /llvm/lib/MC/MCStreamer.cpp | |
| parent | bb9caf73fa33cc4c7cec11155e5737339547c28b (diff) | |
| download | bcm5719-llvm-d6a7301c78efdf8193af9ccbc68c0b43ec03908c.tar.gz bcm5719-llvm-d6a7301c78efdf8193af9ccbc68c0b43ec03908c.zip | |
Fix type of last vector operand of Neon quad-register multiple-lane intrinsics.
The sensible thing would be to have these intrinsics take all quad-register
vector operands, but that's not what ARM did. They made the last vector
operand always be a double-register type. Since the lane number
must be a constant, the user can know which half of a quad-register contains
that lane, extract the high or low half of the vector, and adjust the lane
number accordingly. The only advantage I can see for this is that it works
better when you want to multiply a quad-register value by a lane from a
double-register value, but I wouldn't have expected that to be the common
case. Oh well -- at this point we just need to follow the spec.
llvm-svn: 121397
Diffstat (limited to 'llvm/lib/MC/MCStreamer.cpp')
0 files changed, 0 insertions, 0 deletions
