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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-07-14 13:08:14 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-07-14 13:08:14 +0000 |
| commit | 7ddb0ab85f04f56371ae948052188d968725b8b7 (patch) | |
| tree | 1e6a4c8d0784284e475f94b83ab343fae835d748 /llvm/lib/MC/MCSectionCOFF.cpp | |
| parent | d73e7cc8793c8501592161daa9ff307abc432155 (diff) | |
| download | bcm5719-llvm-7ddb0ab85f04f56371ae948052188d968725b8b7.tar.gz bcm5719-llvm-7ddb0ab85f04f56371ae948052188d968725b8b7.zip | |
[mips] For the FP64A ABI, odd-numbered double-precision moves must not use mtc1/mfc1.
Summary:
This is because the FP64A the hardware will redirect 32-bit reads/writes
from/to odd-numbered registers to the upper 32-bits of the corresponding
even register. In effect, simulating FR=0 mode when FR=0 mode is not
available.
Unfortunately, we have to make the decision to avoid mfc1/mtc1 before
register allocation so we currently do this for even registers too.
FPXX has a similar requirement on 32-bit architectures that lack
mfhc1/mthc1 so this patch also handles the affected moves from the FPU for
FPXX too. Moves to the FPU were supported by an earlier commit.
Differential Revision: http://reviews.llvm.org/D4484
llvm-svn: 212938
Diffstat (limited to 'llvm/lib/MC/MCSectionCOFF.cpp')
0 files changed, 0 insertions, 0 deletions
