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| author | Matthias Braun <matze@braunis.de> | 2015-11-17 00:50:55 +0000 |
|---|---|---|
| committer | Matthias Braun <matze@braunis.de> | 2015-11-17 00:50:55 +0000 |
| commit | fe9d6f211f0b0b4beed7abd97c9e59057477234c (patch) | |
| tree | fd51e83ab8831b882e22f053732d2d837521feed /llvm/lib/MC/MCObjectFileInfo.cpp | |
| parent | cdec7ee565e5bcf399537c0dc218a4fdaba5fdac (diff) | |
| download | bcm5719-llvm-fe9d6f211f0b0b4beed7abd97c9e59057477234c.tar.gz bcm5719-llvm-fe9d6f211f0b0b4beed7abd97c9e59057477234c.zip | |
Assume lane masks are always precise
Allowing imprecise lane masks in case of more than 32 sub register lanes
lead to some tricky corner cases, and I need another bugfix for another
one. Instead I rather declare lane masks as precise and let tablegen
abort if we do not have enough bits.
This does not affect any in-tree target, even AMDGPU only needs 16 lanes
at the moment. If the 32 lanes turn out to be a problem in the future,
then we can easily change the LaneBitmask typedef to uint64_t.
Differential Revision: http://reviews.llvm.org/D14557
llvm-svn: 253279
Diffstat (limited to 'llvm/lib/MC/MCObjectFileInfo.cpp')
0 files changed, 0 insertions, 0 deletions
