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| author | Sander de Smalen <sander.desmalen@arm.com> | 2019-11-05 16:54:54 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2019-11-11 09:03:19 +0000 |
| commit | 84a0c8e3ae92829c4f04ba995b4b6283d397f65d (patch) | |
| tree | 0bbb41cd76861bd92e2a0c3a56b4e3a15e6dc350 /llvm/lib/IR | |
| parent | 06456daa9e59ffddc634e4f1aa592161653fbd36 (diff) | |
| download | bcm5719-llvm-84a0c8e3ae92829c4f04ba995b4b6283d397f65d.tar.gz bcm5719-llvm-84a0c8e3ae92829c4f04ba995b4b6283d397f65d.zip | |
[AArch64][SVE] Spilling/filling of SVE callee-saves.
Implement the spills/fills of callee-saved SVE registers using STR and LDR
instructions.
Also adds the `aarch64_sve_vector_pcs` attribute to specify the
callee-saved registers to be used for functions that return SVE vectors or
take SVE vectors as arguments. The callee-saved registers are vector
registers z8-z23 and predicate registers p4-p15.
The overal frame-layout with SVE will be as follows:
+-------------+
| stack args |
+-------------+
| Callee Saves|
| X29, X30 |
|-------------| <- FP
| SVE Callee | < //////////////
| saved regs | < //////////////
| z23 | < //////////////
| : | < // SCALABLE //
| z8 | < //////////////
| p15 | < /// STACK ////
| : | < //////////////
| p4 | < //// AREA ////
+-------------+ < //////////////
| : | < //////////////
| SVE locals | < //////////////
| : | < //////////////
+-------------+
|/////////////| alignment gap.
| : |
| Stack objs |
| : |
+-------------+ <- SP after call and frame-setup
Reviewers: cameron.mcinally, efriedma, greened, thegameg, ostannard, rengolin
Reviewed By: ostannard
Differential Revision: https://reviews.llvm.org/D68996
Diffstat (limited to 'llvm/lib/IR')
| -rw-r--r-- | llvm/lib/IR/AsmWriter.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp index 107b32ea326..5ee0d52fe99 100644 --- a/llvm/lib/IR/AsmWriter.cpp +++ b/llvm/lib/IR/AsmWriter.cpp @@ -364,6 +364,9 @@ static void PrintCallingConv(unsigned cc, raw_ostream &Out) { case CallingConv::ARM_AAPCS: Out << "arm_aapcscc"; break; case CallingConv::ARM_AAPCS_VFP: Out << "arm_aapcs_vfpcc"; break; case CallingConv::AArch64_VectorCall: Out << "aarch64_vector_pcs"; break; + case CallingConv::AArch64_SVE_VectorCall: + Out << "aarch64_sve_vector_pcs"; + break; case CallingConv::MSP430_INTR: Out << "msp430_intrcc"; break; case CallingConv::AVR_INTR: Out << "avr_intrcc "; break; case CallingConv::AVR_SIGNAL: Out << "avr_signalcc "; break; |
