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authorAhmed Bougacha <ahmed.bougacha@gmail.com>2014-12-01 20:59:00 +0000
committerAhmed Bougacha <ahmed.bougacha@gmail.com>2014-12-01 20:59:00 +0000
commitd0ce058f2ce944d32ad140465b6a74316510d269 (patch)
tree99a76cf463da49cea58f438a76dd6bda5a102fdc /llvm/lib/IR/Verifier.cpp
parent879463206e16eb0a03dd86c14aeba792355dea47 (diff)
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[AArch64] Don't combine "select (setcc i1 LHS, RHS), vL, vR".
r208210 introduced an optimization that improves the vector select codegen by doing the setcc on vectors directly. This is a problem they the setcc operands are i1s, because the optimization would create vectors of i1, which aren't legal. Part of PR21549. Differential Revision: http://reviews.llvm.org/D6308 llvm-svn: 223075
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