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author | Asiri Rathnayake <asiri.rathnayake@arm.com> | 2014-12-05 16:33:56 +0000 |
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committer | Asiri Rathnayake <asiri.rathnayake@arm.com> | 2014-12-05 16:33:56 +0000 |
commit | fd4a6b7f193c22db8566b9d74b470d5d036912f6 (patch) | |
tree | 3e18fce888b9031d10092ef1a8f12a68bf67f949 /llvm/lib/IR/LLVMContextImpl.h | |
parent | 879aeb776c0bdba49e2de9f02eb7aae279e54542 (diff) | |
download | bcm5719-llvm-fd4a6b7f193c22db8566b9d74b470d5d036912f6.tar.gz bcm5719-llvm-fd4a6b7f193c22db8566b9d74b470d5d036912f6.zip |
Improvements to ARM assembler tests
No functional changes. Got myself bitten in r223113 when adding support for
modified immediate syntax (regressions reported by joerg@britannica.bec.de,
fixes in r223366 and r223381). Our assembler tests did not cover serveral
different syntax variants. This patch expands the test coverage to check for
the following cases:
1. Modified immediate operands may be expressed with expressions, as in #(4 * 2)
instead of #8.
2. Modified immediate operands may be _optionally_ prefixed by a '#' symbol or a
'$' symbol.
3. Certain instructions (e.g. ADD) support single input register variants;
[ADD r0, #mod_imm] is same as [ADD r0, r0, #mod_imm].
4. Certain instructions have aliases which convert plain immediates to modified
immediates. For an example, [ADD r0, -10] is not valid because -10 (in two's
complement) cannot be encoded as a modified immediate, but ARMInstrInfo.td
defines an alias which can transform this into a [SUB r0, 10].
llvm-svn: 223475
Diffstat (limited to 'llvm/lib/IR/LLVMContextImpl.h')
0 files changed, 0 insertions, 0 deletions