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authorAndrew Kaylor <andrew.kaylor@intel.com>2013-04-24 22:39:12 +0000
committerAndrew Kaylor <andrew.kaylor@intel.com>2013-04-24 22:39:12 +0000
commitf91b5acc993a1a5a838e035303a22d874ea4a9f3 (patch)
treedc8bf76f3a053fde660ef0019ad4bc168a1e57ff /llvm/lib/ExecutionEngine
parentf4d6de6a5385e18e0b7746d3037f2029069c6ef3 (diff)
downloadbcm5719-llvm-f91b5acc993a1a5a838e035303a22d874ea4a9f3.tar.gz
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Making invalidateInstructionCache automatic in SectionMemoryManager
llvm-svn: 180225
Diffstat (limited to 'llvm/lib/ExecutionEngine')
-rw-r--r--llvm/lib/ExecutionEngine/MCJIT/SectionMemoryManager.cpp5
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/ExecutionEngine/MCJIT/SectionMemoryManager.cpp b/llvm/lib/ExecutionEngine/MCJIT/SectionMemoryManager.cpp
index fa35acd389a..da931247b6c 100644
--- a/llvm/lib/ExecutionEngine/MCJIT/SectionMemoryManager.cpp
+++ b/llvm/lib/ExecutionEngine/MCJIT/SectionMemoryManager.cpp
@@ -138,6 +138,11 @@ bool SectionMemoryManager::applyPermissions(std::string *ErrMsg)
// Read-write data memory already has the correct permissions
+ // Some platforms with separate data cache and instruction cache require
+ // explicit cache flush, otherwise JIT code manipulations (like resolved
+ // relocations) will get to the data cache but not to the instruction cache.
+ invalidateInstructionCache();
+
return false;
}
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