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author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-11-06 09:53:05 +0000 |
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committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-11-06 09:53:05 +0000 |
commit | 66e799ff1b5b31300fbe06185fac81c4402fe18a (patch) | |
tree | 8cbef91566d7142bb22ea298c28110891bfe62fe /llvm/lib/ExecutionEngine/RuntimeDyld/Targets | |
parent | 3400563ea6160dce01a0fb4741bacc4b61db74ad (diff) | |
download | bcm5719-llvm-66e799ff1b5b31300fbe06185fac81c4402fe18a.tar.gz bcm5719-llvm-66e799ff1b5b31300fbe06185fac81c4402fe18a.zip |
[JIT] Fix more missing endian conversions (opcodes for AArch64, ARM, and Mips stub functions, and ARM target in general)
Summary:
Fixed all of the missing endian conversions that Lang Hames and I identified in
RuntimeDyldMachOARM.h.
Fixed the opcode emission in RuntimeDyldImpl::createStubFunction() for AArch64,
ARM, Mips when the host endian doesn't match the target endian.
PowerPC will need changing if it's opcodes are affected by endianness but I've
left this for now since I'm unsure if this is the case and it's the only path
that specifies the target endian.
This patch fixes MachO_ARM_PIC_relocations.s on a big-endian Mips host. This
is the last of the known issues on this host.
Reviewers: lhames
Reviewed By: lhames
Subscribers: aemerson, llvm-commits
Differential Revision: http://reviews.llvm.org/D6130
llvm-svn: 221446
Diffstat (limited to 'llvm/lib/ExecutionEngine/RuntimeDyld/Targets')
-rw-r--r-- | llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOARM.h | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOARM.h b/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOARM.h index 9f5b573920d..9766751c43d 100644 --- a/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOARM.h +++ b/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOARM.h @@ -39,8 +39,7 @@ public: default: return memcpyAddend(RE); case MachO::ARM_RELOC_BR24: { - uint32_t Temp; - memcpy(&Temp, LocalAddress, 4); + uint32_t Temp = readBytesUnaligned(LocalAddress, 4); Temp &= 0x00ffffff; // Mask out the opcode. // Now we've got the shifted immediate, shift by 2, sign extend and ret. return SignExtend32<26>(Temp << 2); @@ -112,7 +111,6 @@ public: case MachO::ARM_RELOC_BR24: { // Mask the value into the target address. We know instructions are // 32-bit aligned, so we can do it all at once. - uint32_t *p = (uint32_t *)LocalAddress; Value += RE.Addend; // The low two bits of the value are not encoded. Value >>= 2; @@ -123,7 +121,9 @@ public: // instruction instead. // Insert the value into the instruction. - *p = (*p & ~0xffffff) | FinalValue; + uint32_t Temp = readBytesUnaligned(LocalAddress, 4); + writeBytesUnaligned((Temp & ~0xffffff) | FinalValue, LocalAddress, 4); + break; } case MachO::ARM_RELOC_HALF_SECTDIFF: { @@ -136,10 +136,9 @@ public: Value = (Value >> 16); Value &= 0xffff; - uint32_t Insn; - memcpy(&Insn, LocalAddress, 4); + uint32_t Insn = readBytesUnaligned(LocalAddress, 4); Insn = (Insn & 0xfff0f000) | ((Value & 0xf000) << 4) | (Value & 0x0fff); - memcpy(LocalAddress, &Insn, 4); + writeBytesUnaligned(Insn, LocalAddress, 4); break; } @@ -222,8 +221,7 @@ private: uint64_t Offset; RelI->getOffset(Offset); uint8_t *LocalAddress = Section.Address + Offset; - int64_t Immediate = 0; - memcpy(&Immediate, LocalAddress, 4); // Copy the whole instruction out. + int64_t Immediate = readBytesUnaligned(LocalAddress, 4); // Copy the whole instruction out. Immediate = ((Immediate >> 4) & 0xf000) | (Immediate & 0xfff); ++RelI; |