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| author | Simon Tatham <simon.tatham@arm.com> | 2019-06-10 14:43:55 +0000 |
|---|---|---|
| committer | Simon Tatham <simon.tatham@arm.com> | 2019-06-10 14:43:55 +0000 |
| commit | b87669f166ce0bb810b2a6655fdaa79bc3b4f010 (patch) | |
| tree | 72c6bc4c05eb42e6a74488aa87363599019c8690 /llvm/lib/ExecutionEngine/ExecutionEngine.cpp | |
| parent | ce49e2231bb6096f2a859b939243efdec85c1ca1 (diff) | |
| download | bcm5719-llvm-b87669f166ce0bb810b2a6655fdaa79bc3b4f010.tar.gz bcm5719-llvm-b87669f166ce0bb810b2a6655fdaa79bc3b4f010.zip | |
[ARM] Disallow PC, and optionally SP, in VMOVRH and VMOVHR.
Arm v8.1-M supports the VMOV instructions that move a half-precision
value to and from a GPR, but not if the GPR is SP or PC.
To fix this, I've changed those instructions to use the rGPR register
class instead of GPR. rGPR always excludes PC, and it excludes SP
except in the presence of the HasV8Ops target feature (i.e. Arm v8-A).
So the effect is that VMOV.F16 to and from PC is now illegal
everywhere, but VMOV.F16 to and from SP is illegal only on non-v8-A
cores (which I believe is all as it should be).
Reviewers: dmgreen, samparker, SjoerdMeijer, ostannard
Reviewed By: ostannard
Subscribers: ostannard, javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60704
llvm-svn: 362942
Diffstat (limited to 'llvm/lib/ExecutionEngine/ExecutionEngine.cpp')
0 files changed, 0 insertions, 0 deletions
