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authorCraig Topper <craig.topper@intel.com>2019-06-10 00:41:07 +0000
committerCraig Topper <craig.topper@intel.com>2019-06-10 00:41:07 +0000
commitf7ba8b808a89d5e050deb7dbd77004fa8e0dff9b (patch)
tree51b045badd2ad9e909b3bf0a49c784fc713b5fa9 /llvm/lib/DebugInfo/PDB/PDBSymbolThunk.cpp
parent80fee25776c2fb61e74c1ecb1a523375c2500b69 (diff)
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[X86] Convert f32/f64 FANDN/FAND/FOR/FXOR to vector logic ops and scalar_to_vector/extract_vector_elts to reduce isel patterns.
Previously we did the equivalent operation in isel patterns with COPY_TO_REGCLASS operations to transition. By inserting scalar_to_vetors and extract_vector_elts before isel we can allow each piece to be selected individually and accomplish the same final result. I ideally we'd use vector operations earlier in lowering/combine, but that looks to be more difficult. The scalar-fp-to-i64.ll changes are because we have a pattern for using movlpd for store+extract_vector_elt. While an f64 store uses movsd. The encoding sizes are the same. llvm-svn: 362914
Diffstat (limited to 'llvm/lib/DebugInfo/PDB/PDBSymbolThunk.cpp')
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