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| author | Hiroshi Inoue <inouehrs@jp.ibm.com> | 2017-06-29 18:03:28 +0000 |
|---|---|---|
| committer | Hiroshi Inoue <inouehrs@jp.ibm.com> | 2017-06-29 18:03:28 +0000 |
| commit | ff8453db567cf6ccd3172ea41cef982fe4c74d29 (patch) | |
| tree | 7469049159786da87bfad3ed12d49c30818bb81f /llvm/lib/CodeGen | |
| parent | 743de46043d2e35eb6034537648d3893c9834ae6 (diff) | |
| download | bcm5719-llvm-ff8453db567cf6ccd3172ea41cef982fe4c74d29.tar.gz bcm5719-llvm-ff8453db567cf6ccd3172ea41cef982fe4c74d29.zip | |
fix trivial typo, NFC
llvm-svn: 306716
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/RegAllocGreedy.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp index 50d241bff23..9562652556a 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -2622,7 +2622,7 @@ unsigned RAGreedy::selectOrSplitImpl(LiveInterval &VirtReg, } // If we couldn't allocate a register from spilling, there is probably some - // invalid inline assembly. The base class wil report it. + // invalid inline assembly. The base class will report it. if (Stage >= RS_Done || !VirtReg.isSpillable()) return tryLastChanceRecoloring(VirtReg, Order, NewVRegs, FixedRegisters, Depth); |
