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authorAndrew Trick <atrick@apple.com>2012-12-05 21:37:50 +0000
committerAndrew Trick <atrick@apple.com>2012-12-05 21:37:50 +0000
commitfda7a8832d6fc78b10a5c0eb40b8a29518b8faec (patch)
tree9574a69201544d678d02dbe7ceb346cfefbc855f /llvm/lib/CodeGen
parent7bbcad7bcd9c2c5818a21a37d6d33ca791ece332 (diff)
downloadbcm5719-llvm-fda7a8832d6fc78b10a5c0eb40b8a29518b8faec.tar.gz
bcm5719-llvm-fda7a8832d6fc78b10a5c0eb40b8a29518b8faec.zip
RegisterPressureTracker: fix findUseBetween to handle DebugValue
llvm-svn: 169427
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/RegisterPressure.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp
index 1576b2abbe3..c7859b9395c 100644
--- a/llvm/lib/CodeGen/RegisterPressure.cpp
+++ b/llvm/lib/CodeGen/RegisterPressure.cpp
@@ -680,6 +680,8 @@ static bool findUseBetween(unsigned Reg,
UI = MRI->use_nodbg_begin(Reg), UE = MRI->use_nodbg_end();
UI != UE; UI.skipInstruction()) {
const MachineInstr* MI = &*UI;
+ if (MI->isDebugValue())
+ continue;
SlotIndex InstSlot = LIS->getInstructionIndex(MI).getRegSlot();
if (InstSlot >= PriorUseIdx && InstSlot < NextUseIdx)
return true;
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