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author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-12-11 11:08:40 +0000 |
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committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-12-11 11:08:40 +0000 |
commit | f6371f5f23ab2f4cddfe7e30185a7bbe2265e0b2 (patch) | |
tree | 7588903fe3b4cbd2cfbdba21ee91c0c3af6ac0c9 /llvm/lib/CodeGen | |
parent | ec338c9dd3b64b65a03628d1f262dfdcb472ebf5 (diff) | |
download | bcm5719-llvm-f6371f5f23ab2f4cddfe7e30185a7bbe2265e0b2.tar.gz bcm5719-llvm-f6371f5f23ab2f4cddfe7e30185a7bbe2265e0b2.zip |
[TargetLowering] Add ISD::EXTRACT_VECTOR_ELT support to SimplifyDemandedBits
Let SimplifyDemandedBits attempt to simplify all elements of a vector extraction.
Part of PR39689.
llvm-svn: 348839
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 1f5ea31c815..6d0d392b8f4 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1220,6 +1220,25 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, Known.Zero |= ~InMask; break; } + case ISD::EXTRACT_VECTOR_ELT: { + // Demand the bits from every vector element. + SDValue Src = Op.getOperand(0); + unsigned EltBitWidth = Src.getScalarValueSizeInBits(); + + // If BitWidth > EltBitWidth the value is anyext:ed. So we do not know + // anything about the extended bits. + APInt DemandedSrcBits = DemandedBits; + if (BitWidth > EltBitWidth) + DemandedSrcBits = DemandedSrcBits.trunc(EltBitWidth); + + if (SimplifyDemandedBits(Src, DemandedSrcBits, Known2, TLO, Depth + 1)) + return true; + + Known = Known2; + if (BitWidth > EltBitWidth) + Known = Known.zext(BitWidth); + break; + } case ISD::BITCAST: { SDValue Src = Op.getOperand(0); EVT SrcVT = Src.getValueType(); |