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author | Craig Topper <craig.topper@intel.com> | 2019-02-20 18:47:26 +0000 |
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committer | Craig Topper <craig.topper@intel.com> | 2019-02-20 18:47:26 +0000 |
commit | f4923db5a3ff15d69b6538334fa149aaccd75dee (patch) | |
tree | 605fb66f6df10c414b22bbf822b94e7d5c4cfd2e /llvm/lib/CodeGen | |
parent | f8498a615b8f0b728fcbc227acba3c38e1024e64 (diff) | |
download | bcm5719-llvm-f4923db5a3ff15d69b6538334fa149aaccd75dee.tar.gz bcm5719-llvm-f4923db5a3ff15d69b6538334fa149aaccd75dee.zip |
Revert r354498 "[X86] Add test case to show missed opportunity to remove an explicit AND on the bit position from BT when it has known zeros."
I accidentally committed more than just the test.
llvm-svn: 354499
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index de69099d03d..d7d7b8b7191 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2102,13 +2102,9 @@ SDValue SelectionDAG::GetDemandedBits(SDValue V, const APInt &Mask) { break; case ISD::AND: { // X & -1 -> X (ignoring bits which aren't demanded). - // Also handle the case where masked out bits in X are known to be zero. - if (ConstantSDNode *RHSC = isConstOrConstSplat(V.getOperand(1))) { - const APInt &AndVal = RHSC->getAPIntValue(); - if (Mask.isSubsetOf(AndVal) || - Mask.isSubsetOf(computeKnownBits(V.getOperand(0)).Zero | AndVal)) - return V.getOperand(0); - } + ConstantSDNode *AndVal = isConstOrConstSplat(V.getOperand(1)); + if (AndVal && Mask.isSubsetOf(AndVal->getAPIntValue())) + return V.getOperand(0); break; } case ISD::ANY_EXTEND: { |