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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-05-17 18:36:31 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-05-17 18:36:31 +0000 |
| commit | f3cedf4823cedc2d073e1d278d1044198c049a7b (patch) | |
| tree | 014806863365a6a52cff0460564e4340b0375e28 /llvm/lib/CodeGen | |
| parent | bebc7d6a4e5dc0531f51dc98a085d1a9170351b3 (diff) | |
| download | bcm5719-llvm-f3cedf4823cedc2d073e1d278d1044198c049a7b.tar.gz bcm5719-llvm-f3cedf4823cedc2d073e1d278d1044198c049a7b.zip | |
GlobalISel: Define integer min/max instructions
Doesn't attempt to emit them for anything yet, but some legalizations
I want to port use them.
llvm-svn: 361061
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index 524031659bb..d58a4629815 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -901,7 +901,11 @@ MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc, case TargetOpcode::G_UDIV: case TargetOpcode::G_SDIV: case TargetOpcode::G_UREM: - case TargetOpcode::G_SREM: { + case TargetOpcode::G_SREM: + case TargetOpcode::G_SMIN: + case TargetOpcode::G_SMAX: + case TargetOpcode::G_UMIN: + case TargetOpcode::G_UMAX: { // All these are binary ops. assert(DstOps.size() == 1 && "Invalid Dst"); assert(SrcOps.size() == 2 && "Invalid Srcs"); |
