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author | Aditya Nandakumar <aditya_nandakumar@apple.com> | 2018-01-24 01:35:26 +0000 |
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committer | Aditya Nandakumar <aditya_nandakumar@apple.com> | 2018-01-24 01:35:26 +0000 |
commit | f2aa2af24e9d635189ffbc0ea797977e845466e9 (patch) | |
tree | 16cc258ff2b8ce2b384a95d63f654c3eb58e1d67 /llvm/lib/CodeGen | |
parent | 23012e98c94989febc5334de85f8c18ba19f0097 (diff) | |
download | bcm5719-llvm-f2aa2af24e9d635189ffbc0ea797977e845466e9.tar.gz bcm5719-llvm-f2aa2af24e9d635189ffbc0ea797977e845466e9.zip |
[GISel]: Remove redundant copies at the end of ISel
https://reviews.llvm.org/D42402
A lot of these copies are useless (copies b/w VRegs having the same
regclass) and should be cleaned up.
llvm-svn: 323291
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r-- | llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp index 422cc2219aa..301233073b1 100644 --- a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp +++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp @@ -159,6 +159,38 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) { const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); + for (MachineBasicBlock &MBB : MF) { + if (MBB.empty()) + continue; + + // Try to find redundant copies b/w vregs of the same register class. + bool ReachedBegin = false; + for (auto MII = std::prev(MBB.end()), Begin = MBB.begin(); !ReachedBegin;) { + // Select this instruction. + MachineInstr &MI = *MII; + + // And have our iterator point to the next instruction, if there is one. + if (MII == Begin) + ReachedBegin = true; + else + --MII; + if (MI.getOpcode() != TargetOpcode::COPY) + continue; + unsigned SrcReg = MI.getOperand(1).getReg(); + unsigned DstReg = MI.getOperand(0).getReg(); + if (TargetRegisterInfo::isVirtualRegister(SrcReg) && + TargetRegisterInfo::isVirtualRegister(DstReg)) { + MachineRegisterInfo &MRI = MF.getRegInfo(); + auto SrcRC = MRI.getRegClass(SrcReg); + auto DstRC = MRI.getRegClass(DstReg); + if (SrcRC == DstRC) { + MRI.replaceRegWith(DstReg, SrcReg); + MI.eraseFromParentAndMarkDBGValuesForRemoval(); + } + } + } + } + // Now that selection is complete, there are no more generic vregs. Verify // that the size of the now-constrained vreg is unchanged and that it has a // register class. |