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| author | Chris Lattner <sabre@nondot.org> | 2005-04-11 20:08:52 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-04-11 20:08:52 +0000 |
| commit | edd197062f31d66dec0e5ce669fd59624ad59690 (patch) | |
| tree | 5b88b1addb23c9b7fc396df6d043b5bc9cdf9c3f /llvm/lib/CodeGen | |
| parent | 607bd26b38d2aef28407bb40046db92dd16449d4 (diff) | |
| download | bcm5719-llvm-edd197062f31d66dec0e5ce669fd59624ad59690.tar.gz bcm5719-llvm-edd197062f31d66dec0e5ce669fd59624ad59690.zip | |
Fix expansion of shifts by exactly NVT bits on arch's (like X86) that have
masking shifts.
This fixes the miscompilation of this:
long long test1(unsigned A, unsigned B) {
return ((unsigned long long)A << 32) | B;
}
into this:
test1:
movl 4(%esp), %edx
movl %edx, %eax
orl 8(%esp), %eax
ret
allowing us to generate this instead:
test1:
movl 4(%esp), %edx
movl 8(%esp), %eax
ret
llvm-svn: 21230
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index e1d9836f812..e4213171724 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1500,6 +1500,9 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, } else if (Cst > NVTBits) { Lo = DAG.getConstant(0, NVT); Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); + } else if (Cst == NVTBits) { + Lo = DAG.getConstant(0, NVT); + Hi = InL; } else { Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); Hi = DAG.getNode(ISD::OR, NVT, @@ -1514,6 +1517,9 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, } else if (Cst > NVTBits) { Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); Hi = DAG.getConstant(0, NVT); + } else if (Cst == NVTBits) { + Lo = InH; + Hi = DAG.getConstant(0, NVT); } else { Lo = DAG.getNode(ISD::OR, NVT, DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), @@ -1530,6 +1536,10 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, DAG.getConstant(Cst-NVTBits, ShTy)); Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(NVTBits-1, ShTy)); + } else if (Cst == NVTBits) { + Lo = InH; + Hi = DAG.getNode(ISD::SRA, NVT, InH, + DAG.getConstant(NVTBits-1, ShTy)); } else { Lo = DAG.getNode(ISD::OR, NVT, DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), |
