diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-02-18 22:39:22 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-02-18 22:39:22 +0000 |
| commit | e84bdce60998f2d0236317e9b44b98865d337d86 (patch) | |
| tree | cc015c22d2ae93f48c8e5a042bee59ff63c656b3 /llvm/lib/CodeGen | |
| parent | cd8607db2d25f96c36b5eac6406f39ac15ac8894 (diff) | |
| download | bcm5719-llvm-e84bdce60998f2d0236317e9b44b98865d337d86.tar.gz bcm5719-llvm-e84bdce60998f2d0236317e9b44b98865d337d86.zip | |
GlobalISel: Make buildExtract use DstOp/SrcOp
llvm-svn: 354292
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 27 |
1 files changed, 15 insertions, 12 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index c01eee1fe88..d73cd6c782d 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -452,26 +452,29 @@ MachineInstrBuilder MachineIRBuilder::buildCast(const DstOp &Dst, return buildInstr(Opcode, Dst, Src); } -MachineInstrBuilder MachineIRBuilder::buildExtract(unsigned Res, unsigned Src, +MachineInstrBuilder MachineIRBuilder::buildExtract(const DstOp &Dst, + const SrcOp &Src, uint64_t Index) { + LLT SrcTy = Src.getLLTTy(*getMRI()); + LLT DstTy = Dst.getLLTTy(*getMRI()); + #ifndef NDEBUG - assert(getMRI()->getType(Src).isValid() && "invalid operand type"); - assert(getMRI()->getType(Res).isValid() && "invalid operand type"); - assert(Index + getMRI()->getType(Res).getSizeInBits() <= - getMRI()->getType(Src).getSizeInBits() && + assert(SrcTy.isValid() && "invalid operand type"); + assert(DstTy.isValid() && "invalid operand type"); + assert(Index + DstTy.getSizeInBits() <= SrcTy.getSizeInBits() && "extracting off end of register"); #endif - if (getMRI()->getType(Res).getSizeInBits() == - getMRI()->getType(Src).getSizeInBits()) { + if (DstTy.getSizeInBits() == SrcTy.getSizeInBits()) { assert(Index == 0 && "insertion past the end of a register"); - return buildCast(Res, Src); + return buildCast(Dst, Src); } - return buildInstr(TargetOpcode::G_EXTRACT) - .addDef(Res) - .addUse(Src) - .addImm(Index); + auto Extract = buildInstr(TargetOpcode::G_EXTRACT); + Dst.addDefToMIB(*getMRI(), Extract); + Src.addSrcToMIB(Extract); + Extract.addImm(Index); + return Extract; } void MachineIRBuilder::buildSequence(unsigned Res, ArrayRef<unsigned> Ops, |

